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001			ocn764691581
003			OCoLC
005			20220713083321.0
006			m o d
007			cr cnu---unuuu
008			111130s2011 enka ob 001 0 eng d
010			_a 2010048032
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020			_a9781119991144 _q(electronic bk.)
020			_a1119991145 _q(electronic bk.)
020			_z9780470685716
020			_z0470685719
020			_z1119991145
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020			_z1119991137
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037			_aCL0500000213 _bSafari Books Online
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084			_aTEC008010 _2bisacsh
049			_aMAIN
100	1		_aVoldman, Steven H. _9157188
245	1	0	_aESD : _bdesign and synthesis / _cSteven H. Voldman.
260			_aChichester, West Sussex, U.K. : _bWiley, _c2011.
300			_a1 online resource (xx, 270 pages) : _billustrations
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
490	1		_aESD series
504			_aIncludes bibliographical references and index.
520			_a"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"-- _cProvided by publisher
505	0	0	_gMachine generated contents note: _g1. _tESD Design Synthesis -- _g1.1. _tESD Design Synthesis and Architecture Flow -- _g1.1.1. _tTop-Down ESD Design -- _g1.1.2. _tBottom-Up ESD Design -- _g1.1.3. _tTop-Down ESD Design -- Memory Semiconductor Chips -- _g1.1.4. _tTop-Down ESD Design -- ASIC Design System -- _g1.2. _tESD Design -- The Signal Path and the Alternate Current Path -- _g1.3. _tESD Electrical Circuit and Schematic Architecture Concepts -- _g1.3.1. _tThe Ideal ESD Network and the Current -- Voltage DC Design Window -- _g1.3.2. _tThe ESD Design Window -- _g1.3.3. _tThe Ideal ESD Networks in the Frequency Domain Design Window -- _g1.4. _tMapping Semiconductor Chips and ESD Designs -- _g1.4.1. _tMapping Across Semiconductor Fabricators -- _g1.4.2. _tESD Design Mapping Across Technology Generations -- _g1.4.3. _tMapping from Bipolar Technology to CMOS Technology -- _g1.4.4. _tMapping from Digital CMOS Technology to Mixed Signal Analog -- Digital CMOS Technology -- _g1.4.5. _tMapping from Bulk CMOS Technology to Silicon on Insulator (SOI) -- _g1.4.6. _tESD Design -- Mapping CMOS to RF CMOS Technology.
505	0	0	_g1.5. _tESD Chip Architecture and ESD Test Standards -- _g1.5.1. _tESD Chip Architecture and ESD Testing -- _g1.6. _tESD Testing -- _g1.6.1. _tESD Qualification Testing -- _g1.6.2. _tESD Test Models -- _g1.6.3. _tESD Characterization Testing -- _g1.6.4. _tTLP Testing -- _g1.7. _tESD Chip Architecture and ESD Alternative Current Paths -- _g1.7.1. _tESD Circuits, I/O, and Cores -- _g1.7.2. _tESD Signal Pin Circuits -- _g1.7.3. _tESD Power Clamp Networks -- _g1.7.4. _tESD Rail-to-Rail Circuits -- _g1.7.5. _tESD Design and Noise -- _g1.7.6. _tInternal Signal Path ESD Networks -- _g1.7.7. _tCross-Domain ESD Networks -- _g1.8. _tESD Networks, Sequencing, and Chip Architecture -- _g1.9. _tESD Design Synthesis -- Latchup-Free ESD Networks -- _g1.10. _tESD Design Concepts -- Buffering -- Inter-Device -- _g1.11. _tESD Design Concepts -- Ballasting -- Inter-Device -- _g1.12. _tESD Design Concepts -- Ballasting -- Intra-Device -- _g1.13. _tESD Design Concepts -- Distributed Load Techniques -- _g1.14. _tESD Design Concepts -- Dummy Circuits -- _g1.15. _tESD Design Concepts -- Power Supply De-Coupling -- _g1.16. _tESD Design Concepts -- Feedback Loop De-Coupling -- _g1.17. _tESD Layout and Floorplan-Related Concepts.
505	0	0	_g1.17.1. _tDesign Symmetry -- _g1.17.2. _tDesign Segmentation -- _g1.17.3. _tESD Design Concepts -- Utilization of Empty Space -- _g1.17.4. _tESD Design Synthesis -- Across Chip Line Width Variation (ACLV) -- _g1.17.5. _tESD Design Concepts -- Dummy Shapes -- _g1.17.6. _tESD Design Concepts -- Dummy Masks -- _g1.17.7. _tESD Design Concepts -- Adjacency -- _g1.18. _tESD Design Concepts -- Analog Circuit Techniques -- _g1.19. _tESD Design Concepts -- Wire Bonds -- _g1.20. _tDesign Rules -- _g1.20.1. _tESD Design Rule Checking (DRC) -- _g1.20.2. _tESD Layout vs. Schematic (LVS) -- _g1.20.3. _tElectrical Resistance Checking (ERC) -- _g1.21. _tSummary and Closing Comments -- _tProblems -- _tReferences -- _g2. _tESD Architecture and Floorplanning -- _g2.1. _tESD Design Floorplan -- _g2.2. _tPeripheral I/O Design -- _g2.2.1. _tPad-Limited Peripheral I/O Design Architecture -- _g2.2.2. _tPad-Limited Peripheral I/O Design Architecture -- Staggered I/O -- _g2.2.3. _tCore-Limited Peripheral I/O Design Architecture -- _g2.3. _tLumped ESD Power Clamp in Peripheral I/O Design Architecture -- _g2.3.1. _tLumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners.
505	0	0	_g2.3.2. _tLumped ESD Power Clamp in Peripheral I/O Design Architecture -- Power Pads -- _g2.4. _tLumped ESD Power Clamp in Peripheral I/O Design Architecture -- Master/Slave ESD Power Clamp System -- _g2.5. _tArray I/O -- _g2.5.1. _tArray I/O -- Off-Chip Driver Banks -- _g2.5.2. _tArray I/O Nibble Architecture -- _g2.5.3. _tArray I/O Pair Architecture -- _g2.5.4. _tArray I/O -- Fully Distributed -- _g2.6. _tESD Architecture -- Dummy Bus Architectures -- _g2.6.1. _tESD Architecture -- Dummy VDD Bus -- _g2.6.2. _tESD Architecture -- Dummy Ground (VSS) Bus -- _g2.7. _tNative Voltage Power Supply Architecture -- _g2.7.1. _tSingle Power Supply Architecture -- _g2.8. _tMixed-Voltage Architecture -- _g2.8.1. _tMixed-Voltage Architecture -- Single Power Supply -- _g2.8.2. _tMixed-Voltage Architecture -- Dual Power Supply -- _g2.9. _tMixed-Signal Architecture -- _g2.9.1. _tMixed-Signal Architecture -- Bipolar -- _g2.9.2. _tMixed-Signal Architecture -- CMOS -- _g2.10. _tMixed-System Architecture -- Digital and Analog CMOS -- _g2.10.1. _tDigital and Analog CMOS Architecture -- _g2.10.2. _tDigital and Analog Floorplan -- Placement of Analog Circuits -- _g2.11. _tMixed-Signal Architecture -- Digital, Analog, and RF Architecture.
505	0	0	_g2.12. _tSummary and Closing Comments -- _tProblems -- _tReferences -- _g3. _tESD Power Grid Design -- _g3.1. _tESD Power Grid -- _g3.1.1. _tESD Power Grid -- Key ESD Design Parameters -- _g3.1.2. _tESD and the Alternative Current Path -- The Role of ESD Power Grid Resistance -- _g3.2. _tSemiconductor Chip Impedance -- _g3.3. _tInterconnect Failure and Dynamic On-Resistance -- _g3.3.1. _tInterconnect Dynamic On-Resistance -- _g3.3.2. _tTi/Al/Ti Interconnect Failure -- _g3.3.3. _tCopper Interconnect Failure -- _g3.3.4. _tMelting Temperature of Interconnect Materials -- _g3.4. _tInterconnect Wire and Via Guidelines -- _g3.4.1. _tInterconnect Wire and Via Guidelines for HBM ESD Events -- _g3.4.2. _tInterconnect Wire and Via Guidelines for MM ESD Events -- _g3.4.3. _tInterconnect Wire and Via Guidelines for CDM ESD Events -- _g3.4.4. _tInterconnect Wire and Via Guidelines for HMM and IEC 61000-4-2 ESD Events -- _g3.4.5. _tWire and Via ESD Metrics -- _g3.5. _tESD Power Grid Resistance -- _g3.5.1. _tPower Grid Design -- ESD Input to Power Grid Resistance -- _g3.5.2. _tESD Input to Power Grid Connections -- Across ESD Bus Resistance -- _g3.5.3. _tPower Grid Design -- ESD Power Clamp to Power Grid Resistance Evaluation.
505	0	0	_g3.5.4. _tPower Grid Design -- Resistance Evaluation -- _g3.5.5. _tPower Grid Design Distribution Representation -- _g3.6. _tPower Grid Layout Design -- _g3.6.1. _tPower Grid Design -- Slotting of Power Grid -- _g3.6.2. _tPower Grid Design -- Segmentation of Power Grids -- _g3.6.3. _tPower Grid Design -- Chip Corners -- _g3.6.4. _tPower Grid Design -- Stacking of Metal Levels -- _g3.6.5. _tPower Grid Design -- Wiring Bays and Weaved Power Bus Designs -- _g3.7. _tESD Specification Power Grid Considerations -- _g3.7.1. _tCDM Specification Power Grid and Interconnect Design Considerations -- _g3.7.2. _tHMM and IEC Specification Power Grid and Interconnect Design Considerations -- _g3.8. _tPower Grid Design Synthesis -- ESD Design Rule Checking Methods -- _g3.8.1. _tPower Grid Design Synthesis -- ESD DRC Methods Using an ESD Virtual Design Level -- _g3.8.2. _tPower Grid Design Synthesis -- ESD DRC Methods Using an ESD Interconnect Parameterized Cell -- _g3.9. _tSummary and Closing Comments -- _tProblems -- _tReferences -- _g4. _tESD Power Clamps -- _g4.1. _tESD Power Clamps -- _g4.1.1. _tClassification of ESD Power Clamps -- _g4.1.2. _tDesign Synthesis of ESD Power Clamp -- Key Design Parameters.
505	0	0	_g4.2. _tDesign Synthesis of ESD Power Clamps -- _g4.2.1. _tTransient Response Frequency Trigger Element and the ESD Frequency Window -- _g4.2.2. _tThe ESD Power Clamp Frequency Design Window -- _g4.2.3. _tDesign Synthesis of ESD Power Clamp -- Voltage Triggered ESD Trigger Elements -- _g4.3. _tDesign Synthesis of ESD Power Clamp -- The ESD Power Clamp Shunting Element -- _g4.3.1. _tESD Power Clamp Trigger Condition vs. Shunt Failure -- _g4.3.2. _tESD Clamp Element -- Width Scaling -- _g4.3.3. _tESD Clamp Element -- On-Resistance -- _g4.3.4. _tESD Clamp Element -- Safe Operating Area -- _g4.4. _tESD Power Clamp Issues -- _g4.4.1. _tESD Power Clamp Issues -- Power-Up and Power-Down -- _g4.4.2. _tESD Power Clamp Issues -- False Triggering -- _g4.4.3. _tESD Power Clamp Issues -- Pre-Charging -- _g4.4.4. _tESD Power Clamp Issues -- Post-Charging -- _g4.5. _tESD Power Clamp Design -- _g4.5.1. _tNative Power Supply RC-Triggered MOSFET ESD Power Clamp -- _g4.5.2. _tNon-Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- _g4.5.3. _tESD Power Clamp Networks with Improved Inverter Stage Feedback -- _g4.5.4. _tESD Power Clamp Design Synthesis -- Forward Bias Triggered ESD Power Clamps.
505	0	0	_g4.5.5. _tESD Power Clamp Design Synthesis -- IEC 61000-4-2 Responsive ESD Power Clamps -- _g4.5.6. _tESD Power Clamp Design Synthesis -- Pre-Charging and Post-Charging Insensitive ESD Power Clamps -- _g4.6. _tESD Power Clamp Design Synthesis -- Bipolar ESD Power Clamps -- _g4.6.1. _tBipolar ESD Power Clamps with Zener Breakdown Trigger Element -- _g4.6.2. _tBipolar ESD Power Clamps with Bipolar Transistor BVceo Breakdown Trigger Element -- _g4.6.3. _tBipolar ESD Power Clamps with BVceo Bipolar Transistor Trigger and Variable Trigger Diode String Network -- _g4.6.4. _tBipolar ESD Power Clamps with Frequency Trigger Elements -- _g4.7. _tMaster/Slave ESD Power Clamp Systems -- _g4.8. _tSummary and Closing Comments -- _tProblems -- _tReferences -- _g5. _tESD Signal Pin Networks Design and Synthesis -- _g5.1. _tESD Signal Pin Structures -- _g5.1.1. _tClassification of ESD Signal Pin Networks -- _g5.1.2. _tESD Design Synthesis of ESD Signal Devices -- Key Design Parameters -- _g5.2. _tESD Input Structures -- ESD and Bond Pads Layout -- _g5.2.1. _tESD and Bond Pad Layout and Synthesis -- _g5.2.2. _tESD Structures Between Bond Pads.
505	0	0	_g5.2.3. _tSplit I/O and Bond Pad -- _g5.2.4. _tSplit ESD Adjacent to Bond Pad -- _g5.2.5. _tESD Structures Partially Under Bond Pads -- _g5.2.6. _tESD Structures Under and Between the Bond Pads -- _g5.2.7. _tESD Circuits and RF Bond Pad Integration -- _g5.2.8. _tRF ESD Signal Pad Structures Under Bond Pads -- _g5.3. _tESD Design Synthesis and Layout of MOSFETs -- _g5.3.1. _tMOSFET Key Design Parameters -- _g5.3.2. _tSingle MOSFET with Silicide Block Masks -- _g5.3.3. _tSeries Cascode MOSFET -- _g5.3.4. _tTriple-well MOSFETs.
505	0	0	_g5.4. _tESD Design Synthesis and Layout of Diodes -- _g5.4.1. _tESD Diode Key Design Parameters -- _g5.4.2. _tESD Design Synthesis of Dual-Diode Networks -- _g5.4.3. _tESD Design Synthesis of Diode String Networks -- _g5.4.4. _tESD Design Synthesis of Back-to-Back Diode String -- _g5.4.5. _tESD Design Synthesis for Differential Pair -- _g5.5. _tESD Design Synthesis of SCRs -- _g5.5.1. _tESD Design Synthesis of Uni-directional SCRs -- _g5.5.2. _tESD Design Synthesis of Bi-directional SCRs -- _g5.5.3. _tESD Design Synthesis of SCRs -- External Trigger Element -- _g5.6. _tESD Design Synthesis and Layout of Resistors -- _g5.6.1. _tPolysilicon Resistor Design Layout -- _g5.6.2. _tDiffusion Resistor Design Layout -- _g5.6.3. _tP-diffusion Resistor Design Layout -- _g5.6.4. _tN-diffusion Resistor Design -- _g5.6.5. _tBuried Resistors -- _g5.6.6. _tN-well Resistors -- _g5.7. _tESD Design Synthesis of Inductors.
505	0	0	_g5.8. _tSummary and Closing Comments -- _tProblems -- _tReferences -- _g6. _tGuard Ring Design and Synthesis -- _g6.1. _tGuard Ring Design and Integration -- _g6.2. _tGuard Ring Characterization -- _g6.2.1. _tGuard Ring Efficiency -- _g6.2.2. _tGuard Ring Theory -- A Generalized Bipolar Transistor Perspective -- _g6.2.3. _tGuard Ring Theory -- A Probability of Escape Perspective -- _g6.2.4. _tGuard Ring -- The Injection Ratio -- _g6.3. _tSemiconductor Chip Guard Ring Seal -- _g6.4. _tI/O to Core Guard Rings -- _g6.5. _tI/O to I/O Guard Rings -- _g6.6. _tWithin I/O Guard Rings -- _g6.6.1. _tWithin I/O Cell Guard Ring -- _g6.6.2. _tESD-to-I/O OCD Guard Ring -- _g6.7. _tESD Signal Pin Guard Rings -- _g6.7.1. _tESD Signal Pin Guard Rings and Dual-Diode ESD Network -- _g6.8. _tLibrary Element Guard Rings -- _g6.8.1. _tN-channel MOSFET Guard Rings -- _g6.8.2. _tP-channel MOSFET Guard Rings -- _g6.8.3. _tRF Guard Rings -- _g6.9. _tMixed-Signal Guard Rings -- Digital to Analog -- _g6.10. _tMixed-Voltage Guard Rings -- High Voltage to Low Voltage.
505	0	0	_g6.10.1. _tGuard Rings -- High Voltage -- _g6.11. _tPassive and Active Guard Rings -- _g6.11.1. _tPassive Guard Rings -- _g6.11.2. _tActive Guard Rings -- _g6.12. _tTrench Guard Rings -- _g6.13. _tTSV Guard Rings -- _g6.14. _tGuard Ring DRC -- _g6.14.1. _tInternal Latchup and Guard Ring Design Rules -- _g6.14.2. _tExternal Latchup Guard Ring Design Rules -- _g6.15. _tGuard Rings and Computer Aided Design Methods -- _g6.15.1. _tBuilt-in Guard Rings -- _g6.15.2. _tGuard Ring Parameterized Cells -- _g6.15.3. _tGuard Ring p-Cell SKILL Code -- _g6.15.4. _tGuard Ring Resistance CAD Design Checking -- _g6.15.5. _tPost-Processing Methodology of Guard Ring Modification -- _g6.16. _tSummary and Closing Comments -- _tProblems -- _tReferences -- _g7. _tESD Full-Chip Design Integration and Architecture -- _g7.1. _tDesign Synthesis and Integration -- _g7.2. _tDigital Design -- _g7.3. _tCustom Design vs. Standard Cell Design -- _g7.4. _tMemory ESD Design -- _g7.4.1. _tDRAM Design -- _g7.4.2. _tSRAM Design -- _g7.4.3. _tNon-Volatile RAM ESD Design -- _g7.5. _tMicroprocessor ESD Design.
505	0	0	_g7.5.1. _t3.3 V Microprocessor with 5.0 V to 3.3 V Interface -- _g7.5.2. _t2.5 V Microprocessor with 5.0 V to 2.5 V Interface -- _g7.5.3. _t1.8 V Microprocessor with 3.3 V to 1.8 V Interface -- _g7.6. _tApplication-Specific Integrated Circuits -- _g7.6.1. _tASIC ESD Design -- _g7.6.2. _tASIC Design Gate Array Standard Cell I/O -- _g7.6.3. _tASIC Design System with Multiple Power Rails -- _g7.6.4. _tASIC Design System with Voltage Islands -- _g7.7. _tCMOS Image Processing Chip Design -- _g7.7.1. _tCMOS Image Processing Chip Design with Long/Narrow Standard Cell -- _g7.7.2. _tCMOS Image Processing Chip Design with Short/Wide Standard Cell -- _g7.8. _tMixed-Signal Architecture -- _g7.8.1. _tMixed-Signal Architecture -- Digital and Analog -- _g7.8.2. _tMixed-Signal Architecture -- Digital, Analog, and RF -- _g7.9. _tSummary and Closing Comments -- _tProblems -- _tReferences.
588	0		_aPrint version record.
590			_aeBooks on EBSCOhost _bEBSCO eBook Subscription Academic Collection - Worldwide
650		0	_aSemiconductors _xProtection. _9272055
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