Network processor design : issues and practices. Volume 1 / edited by Patrick Crowley [and others].
Material type:
TextSeries: Morgan Kaufmann Series in Computer Architecture and DesignPublication details: Burlington : Elsevier, 2002.Description: 1 online resource (353 pages)Content type: - text
- computer
- online resource
- 9780080512495
- 0080512496
- Microprocessors
- Application-specific integrated circuits
- Computer networks -- Equipment and supplies
- Circuits intégrés à la demande
- COMPUTERS -- Logic Design
- TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Logic
- TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- VLSI & ULSI
- Application-specific integrated circuits
- Computer networks -- Equipment and supplies
- Microprocessors
- 621.395 23
- TK7895.M5
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OPJGU Sonepat- Campus | E-Books EBSCO | Available |
Front Cover; Front Cover; Network Processor Design Issues and Practices; Network Processor Design Issues and Practices; Copyright Page; Copyright Page; Contents; Contents; Preface; Preface; Chapter 1. Network Processors: An Introduction to Design Issues; Chapter 1. Network Processors: An Introduction to Design Issues; 1.1 Design Challenges; 1.1 Design Challenges; 1.2 Design Techniques; 1.2 Design Techniques; 1.3 Challenges and Conclusions; 1.3 Challenges and Conclusions; PART I: DESIGN PRINCIPLES; PART I: DESIGN PRINCIPLES; Chapter 2. Benchmarking Network Processors.
Chapter 2. Benchmarking Network ProcessorsChapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing.
Chapter 6. A Network Processor Performance and Design Model with Benchmark ParameterizationChapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 8. A Modeling Framework for Network Processor Systems; Chapter 8. A Modeling Framework for Network Processor Systems; PART II: PRACTICES; PART II: PRACTICES; Chapter 9. An Industry Analyst's Perspective on Networ k Processors.
Chapter 9. An Industry Analyst's Perspective on Networ k ProcessorsChapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 11. Cisco Systems-- Toaster 2; Chapter 11. Cisco Systems-- Toaster 2; Chapter 12. IBM--PowerNP Network Processor; Chapter 12. IBM--PowerNP Network Processor; Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPU.
Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPUChapter 14. Motorola--C-5e Network Processor; Chapter 14. Motorola--C-5e Network Processor; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Index; Index; About the Editors; About the Editors.
As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and dat.
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