Microprocessor architecture : from simple pipelines to chip multiprocessors / Jean-Loup Baer.

By:

Baer, Jean-Loup

Material type: Text

text

Media type:

computer

Carrier type:

online resource

ISBN:

9780511675461
0511675461
9780511672217
0511672217
9780511669361
0511669364
9780511739132
0511739133
9780511671463
0511671466
9786612486708
6612486708
9780511811258
051181125X

Subject(s):

Genre/Form:

Additional physical formats: Print version:: Microprocessor architecture.DDC classification:

004.2/2 22

LOC classification:

QA76.5

Online resources:

Click here to access online

Contents:

Introduction -- The basics -- Superscalar processors -- Front-end : branch predictio, instruction fetching, and register renaming -- Back-end : instruction scheduling, memory access instructions, and clusters -- The cache hierarchy -- Multiprocessors -- Multithreading and (chip) multiprocessing -- Current limitations and future challenges.

Summary: This describes microprocessor architecture, from in-order short pipeline designs to out-of-order superscalars. The emphasis is on how things work at a black box and algorithmic level, with enough detail at the register transfer level to allow appreciation of how design features enhance performance as well as complexity.

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Holdings
Item type	Home library	Collection	Call number	Materials specified	Status	Date due	Barcode
Electronic-Books	OPJGU Sonepat- Campus	E-Books EBSCO			Available

Includes bibliographical references and index.

Print version record.

This describes microprocessor architecture, from in-order short pipeline designs to out-of-order superscalars. The emphasis is on how things work at a black box and algorithmic level, with enough detail at the register transfer level to allow appreciation of how design features enhance performance as well as complexity.

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