Robust design of digital circuits on foil / Kris Myny, Jan Genoe, Wim Dehaene.

Online resource; title from PDF title page (EBSCO, viewed September 19, 2016).

Includes bibliographical references and index.

Cover; Half-title; Title page; Copyright information; Epigraph; Table of contents; Preface; List of abbreviations; 1 Thin-Film Transistor Technologies on the Move? From Backplane Driver to Ubiquitous Circuit Enabler?; 1.1 Backplanes for Active Matrix Displays; 1.1.1 Amorphous Silicon; 1.1.2 Low-Temperature Polycrystalline Silicon; 1.1.3 Organic Thin-Film Transistors; 1.1.4 Metal-Oxide Thin-Film Transistors; 1.1.5 Current TFT Technology Overview; 1.1.6 Options for Flexible Displays; 1.2 Large Area Sensors and Circuits (On Foil); 2 Organic and Metal-Oxide Thin-Film Transistors.

2.1 Device Configurations2.2 Operation Principle; 2.2.1 Operation Principle of a Single-Gate Transistor; 2.2.2 Technology Options for Multiple Threshold Voltages; 2.3 Typical Layout Rules in the Technologies Used in This Book; 2.4 Technologies Used in This Book; 2.4.1 Organic p-Type Technology of Polymer Vision; 2.4.2 Organic p-Type Dual-Gate Technology of Polymer Vision; 2.4.3 Pentacene (p-Type) Thin-Film Transistors on Al2O3 as Gate Dielectric; 2.4.4 a-IGZO (n-Type) Technology on Al2O3 as Gate Dielectric; 2.4.5 Hybrid Complementary Organic/Metal-Oxide Technology.

2.4.6 Hybrid Complementary Organic/Metal-Oxide Technology on PEN-Foil2.5 Trends in Circuit Integration; 2.5.1 Display Periphery; 2.5.2 Digital Logic; 2.5.3 Analog Circuits; 2.6 Summary; 3 Basic Gates; 3.1 Figures-of-Merit; 3.2 Logic Families; 3.3 Unipolar Logic; 3.3.1 Single VT, Depletion-Load, or Zero-VGS-Load Logic; 3.3.1.1 VTC of the Zero-VGS-Load Inverter; 3.3.1.2 Static Parameters of the Zero-VGS-Load Inverter; VM; Gain; 3.3.1.3 Dynamic Behavior of the Zero-VGS-Load Inverter; Study of the Zero-VGS-Load Capacitors; 3.3.2 Dual VT, Zero-VGS-Load Logic by Dual-Gate TFTs.

3.3.2.1 VTC of a Dual-VT Zero-VGS-Load Inverter3.3.2.2 Dual-Gate Zero-VGS-Load Inverter; 3.3.2.3 Optimized Dual-Gate Zero-VGS-Load Inverter; 3.3.3 Single VT, Enhancement-Load, or Diode-Load Logic; 3.3.3.1 VTC of the Diode-Load Inverter; 3.3.3.2 Static Behavior of the Diode-Load Inverter; VM; Gain; 3.3.3.3 Dynamic Behavior of the Diode-Load Inverter; Study of the Diode-Load Capacitances; 3.3.4 Dual VT, Diode-Load Logic in Dual-Gate Technologies; 3.4 Complementary Logic; 3.4.1 VTC of the Complementary Inverter; 3.4.2 Static Behavior of the Complementary Inverter; 3.4.2.1 VM; 3.4.2.2 Gain.

3.4.3 Dynamic Behavior of the Complementary Inverter3.4.3.1 Study of the Complementary Inverter Capacitances; 3.5 Conclusions; 3.6 Suggestions to Improve the Inverter Performance; 3.6.1 Level-Shifter; 3.6.2 Self-Aligned Technology; 4 Variability; 4.1 Classifications; 4.2 Sources of Process Variation; 4.2.1 Semiconductor; 4.2.1.1 Dielectric; 4.2.2 Contacts; 4.2.3 Foil; 4.3 Influence of Parameter Variation on the Yield of Logic Circuits; 4.4 How to Cope with WID and D2D Parameter Variations; 4.4.1 Designing with WID Variations; 4.4.2 Designing with D2D Variations -- Corner Analysis.

A practical guide to the theory and applications of TFT technologies and circuit designs for those in academia and in industry.

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