Network processor design : issues and practices. Volume 2 / edited by Patrick Crowley [and others].

Includes bibliographical references and index.

Print version record.

Front Cover; Network Processor Design Issues and Practices; Copyright Page; About the Editors; Contents; Preface; Chapter 1. Network Processors: Themes and Challenges; 1.1 Technology; 1.2 Programming; 1.3 Applications; 1.4 Challenges and Conclusions; References; PART I: DESIGN PRINCIPLES; Chapter 2. A Programmable, Scalable Platform for Next-Generation Networking; 2.1 The Network Processor Architecture; 2.2 Processor Scheduling; 2.3 Fibre Channel/Infiniband Implementation; 2.4 Performance Simulation and Analysis; 2.5 Conclusions; Acknowledgments; References

Chapter 3. Power Considerations in Network Processor Design3.1 Computational Performance Model; 3.2 Power Model; 3.3 Performance Metrics; 3.4 Design Results; 3.5 Summary and Conclusions; Acknowledgments; References; Chapter 4. Worst-Case Execution Time Estimation for Hardware-Assisted Multithreaded Processors; 4.1 Background and Motivation; 4.2 Processing Throughput of a Single Thread of Execution; 4.3 Processing Throughput of Two Threads; 4.4 Processing Throughput of Four Threads; 4.5 Limitations and Future Work; 4.6 Conclusions; Acknowledgments; References

Chapter 5. Multiprocessor Scheduling in Processor-Based Router Platforms: Issues and Ideas5.1 Related Work and Concepts; 5.2 Issues in Using Pfair Schedulers in Routers; 5.3 Multiprocessor Scheduling in Routers: Key Ideas; 5.4 Experimental Evaluation; 5.5 Conclusions; Acknowledgments; References; Chapter 6. A Massively Multithreaded Packet Processor; 6.1 Random External Memory Accesses; 6.2 Processor/Memory Architectures; 6.3 The Tribe Microarchitecture; 6.4 Network Block; 6.5 Interconnect; 6.6 Project Status; 6.7 Conclusions; References

Chapter 7. Exploring Trade-Offs in Performance and Programmability of Processing Element Topologies for Network Processors7.1 Problem Identification; 7.2 Performance Modeling and Evaluation; 7.3 Topology Exploration for Performance Metrics; 7.4 Interrelation Between Programmability and Topologies; 7.5 Conclusions; Acknowledgments; References; Chapter 8. Packet Classification and Termination in a Protocol Processor; 8.1 Programmable Protocol Processor; 8.2 Control Memory Access Accelerator; 8.3 System Performance; 8.4 Conclusions; 8.5 Further Work; Acknowledgments; References

Chapter 9. NP-Click: A Programming Model for the Intel IXP12009.1 Background; 9.2 Programming Models; 9.3 Description of NP-Click; 9.4 Results; 9.5 Summary and Conclusions; 9.6 Future Work; Acknowledgments; References; Chapter 10. NEPAL: A Framework for Efficiently Structuring Applications for Network Processors; 10.1 Modules; 10.2 NEPAL Design Flow; 10.3 Module Extraction from Sequential Binaries; 10.4 Dynamic Module Manager; 10.5 Discussion; 10.6 Experiments; 10.7 Related Work; 10.8 Conclusions; References

Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network pro.

English.

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