MARC details
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19675cam a2201093 a 4500 |
| 001 - CONTROL NUMBER |
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ocn764691581 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
OCoLC |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20220713083321.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION |
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| fixed length control field |
m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr cnu---unuuu |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
111130s2011 enka ob 001 0 eng d |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2010048032 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
N$T |
| Language of cataloging |
eng |
| Description conventions |
pn |
| Transcribing agency |
N$T |
| Modifying agency |
E7B |
| -- |
EBLCP |
| -- |
OCLCO |
| -- |
OCLCQ |
| -- |
DEBSZ |
| -- |
OCLCQ |
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COO |
| -- |
UMI |
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OCLCQ |
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NLGGC |
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OCLCQ |
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OCLCF |
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YDXCP |
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OCLCQ |
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AZK |
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COCUF |
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MOR |
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LIP |
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PIFAG |
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ZCU |
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MERUC |
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OCLCQ |
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JBG |
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OCLCQ |
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U3W |
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STF |
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WRM |
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VTS |
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CEF |
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NRAMU |
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ICG |
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INT |
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VT2 |
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OCLCQ |
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WYU |
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OCLCQ |
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UAB |
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OCLCQ |
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DKC |
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OCLCQ |
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UKAHL |
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OCLCQ |
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AJS |
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OCLCQ |
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OCLCO |
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UKCRE |
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OCLCO |
| 019 ## - |
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| -- |
841331985 |
| -- |
961503536 |
| -- |
962613542 |
| -- |
988440604 |
| -- |
992026582 |
| -- |
1037702213 |
| -- |
1038579101 |
| -- |
1045443577 |
| -- |
1055380021 |
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1064863357 |
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1081221736 |
| -- |
1103270285 |
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1129334498 |
| -- |
1153009560 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781119991144 |
| Qualifying information |
(electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
1119991145 |
| Qualifying information |
(electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Cancelled/invalid ISBN |
9780470685716 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Cancelled/invalid ISBN |
0470685719 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Cancelled/invalid ISBN |
1119991145 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Cancelled/invalid ISBN |
9781119991137 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Cancelled/invalid ISBN |
1119991137 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Cancelled/invalid ISBN |
9781119992653 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Cancelled/invalid ISBN |
1119992656 |
| 024 8# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
9786613405272 |
| 029 1# - (OCLC) |
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| OCLC library identifier |
AU@ |
| System control number |
000051433039 |
| 029 1# - (OCLC) |
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| OCLC library identifier |
AU@ |
| System control number |
000051556706 |
| 029 1# - (OCLC) |
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AU@ |
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000060532868 |
| 029 1# - (OCLC) |
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AU@ |
| System control number |
000067111181 |
| 029 1# - (OCLC) |
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DEBBG |
| System control number |
BV041121727 |
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DEBBG |
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BV043118761 |
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DEBBG |
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BV044154787 |
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DEBSZ |
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372730264 |
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DEBSZ |
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39676651X |
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DEBSZ |
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421528648 |
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DEBSZ |
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430995172 |
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HEBIS |
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299832961 |
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NZ1 |
| System control number |
14257193 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(OCoLC)764691581 |
| Canceled/invalid control number |
(OCoLC)841331985 |
| -- |
(OCoLC)961503536 |
| -- |
(OCoLC)962613542 |
| -- |
(OCoLC)988440604 |
| -- |
(OCoLC)992026582 |
| -- |
(OCoLC)1037702213 |
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(OCoLC)1038579101 |
| -- |
(OCoLC)1045443577 |
| -- |
(OCoLC)1055380021 |
| -- |
(OCoLC)1064863357 |
| -- |
(OCoLC)1081221736 |
| -- |
(OCoLC)1103270285 |
| -- |
(OCoLC)1129334498 |
| -- |
(OCoLC)1153009560 |
| 037 ## - SOURCE OF ACQUISITION |
|---|
| Stock number |
CL0500000213 |
| Source of stock number/acquisition |
Safari Books Online |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7871.85 |
| Item number |
.V6525 2011eb |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TEC |
| Subject category code subdivision |
008090 |
| Source |
bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TEC |
| Subject category code subdivision |
008100 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815/2 |
| Edition number |
22 |
| 084 ## - OTHER CLASSIFICATION NUMBER |
|---|
| Classification number |
TEC008010 |
| Source of number |
bisacsh |
| 049 ## - LOCAL HOLDINGS (OCLC) |
|---|
| Holding library |
MAIN |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Voldman, Steven H. |
| 9 (RLIN) |
157188 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
ESD : |
| Remainder of title |
design and synthesis / |
| Statement of responsibility, etc |
Steven H. Voldman. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
Chichester, West Sussex, U.K. : |
| Name of publisher, distributor, etc |
Wiley, |
| Date of publication, distribution, etc |
2011. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 online resource (xx, 270 pages) : |
| Other physical details |
illustrations |
| 336 ## - |
|---|
| -- |
text |
| -- |
txt |
| -- |
rdacontent |
| 337 ## - |
|---|
| -- |
computer |
| -- |
c |
| -- |
rdamedia |
| 338 ## - |
|---|
| -- |
online resource |
| -- |
cr |
| -- |
rdacarrier |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
ESD series |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"-- |
| -- |
Provided by publisher |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
Machine generated contents note: |
| -- |
1. |
| Title |
ESD Design Synthesis -- |
| Miscellaneous information |
1.1. |
| Title |
ESD Design Synthesis and Architecture Flow -- |
| Miscellaneous information |
1.1.1. |
| Title |
Top-Down ESD Design -- |
| Miscellaneous information |
1.1.2. |
| Title |
Bottom-Up ESD Design -- |
| Miscellaneous information |
1.1.3. |
| Title |
Top-Down ESD Design -- Memory Semiconductor Chips -- |
| Miscellaneous information |
1.1.4. |
| Title |
Top-Down ESD Design -- ASIC Design System -- |
| Miscellaneous information |
1.2. |
| Title |
ESD Design -- The Signal Path and the Alternate Current Path -- |
| Miscellaneous information |
1.3. |
| Title |
ESD Electrical Circuit and Schematic Architecture Concepts -- |
| Miscellaneous information |
1.3.1. |
| Title |
The Ideal ESD Network and the Current -- Voltage DC Design Window -- |
| Miscellaneous information |
1.3.2. |
| Title |
The ESD Design Window -- |
| Miscellaneous information |
1.3.3. |
| Title |
The Ideal ESD Networks in the Frequency Domain Design Window -- |
| Miscellaneous information |
1.4. |
| Title |
Mapping Semiconductor Chips and ESD Designs -- |
| Miscellaneous information |
1.4.1. |
| Title |
Mapping Across Semiconductor Fabricators -- |
| Miscellaneous information |
1.4.2. |
| Title |
ESD Design Mapping Across Technology Generations -- |
| Miscellaneous information |
1.4.3. |
| Title |
Mapping from Bipolar Technology to CMOS Technology -- |
| Miscellaneous information |
1.4.4. |
| Title |
Mapping from Digital CMOS Technology to Mixed Signal Analog -- Digital CMOS Technology -- |
| Miscellaneous information |
1.4.5. |
| Title |
Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI) -- |
| Miscellaneous information |
1.4.6. |
| Title |
ESD Design -- Mapping CMOS to RF CMOS Technology. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
1.5. |
| Title |
ESD Chip Architecture and ESD Test Standards -- |
| Miscellaneous information |
1.5.1. |
| Title |
ESD Chip Architecture and ESD Testing -- |
| Miscellaneous information |
1.6. |
| Title |
ESD Testing -- |
| Miscellaneous information |
1.6.1. |
| Title |
ESD Qualification Testing -- |
| Miscellaneous information |
1.6.2. |
| Title |
ESD Test Models -- |
| Miscellaneous information |
1.6.3. |
| Title |
ESD Characterization Testing -- |
| Miscellaneous information |
1.6.4. |
| Title |
TLP Testing -- |
| Miscellaneous information |
1.7. |
| Title |
ESD Chip Architecture and ESD Alternative Current Paths -- |
| Miscellaneous information |
1.7.1. |
| Title |
ESD Circuits, I/O, and Cores -- |
| Miscellaneous information |
1.7.2. |
| Title |
ESD Signal Pin Circuits -- |
| Miscellaneous information |
1.7.3. |
| Title |
ESD Power Clamp Networks -- |
| Miscellaneous information |
1.7.4. |
| Title |
ESD Rail-to-Rail Circuits -- |
| Miscellaneous information |
1.7.5. |
| Title |
ESD Design and Noise -- |
| Miscellaneous information |
1.7.6. |
| Title |
Internal Signal Path ESD Networks -- |
| Miscellaneous information |
1.7.7. |
| Title |
Cross-Domain ESD Networks -- |
| Miscellaneous information |
1.8. |
| Title |
ESD Networks, Sequencing, and Chip Architecture -- |
| Miscellaneous information |
1.9. |
| Title |
ESD Design Synthesis -- Latchup-Free ESD Networks -- |
| Miscellaneous information |
1.10. |
| Title |
ESD Design Concepts -- Buffering -- Inter-Device -- |
| Miscellaneous information |
1.11. |
| Title |
ESD Design Concepts -- Ballasting -- Inter-Device -- |
| Miscellaneous information |
1.12. |
| Title |
ESD Design Concepts -- Ballasting -- Intra-Device -- |
| Miscellaneous information |
1.13. |
| Title |
ESD Design Concepts -- Distributed Load Techniques -- |
| Miscellaneous information |
1.14. |
| Title |
ESD Design Concepts -- Dummy Circuits -- |
| Miscellaneous information |
1.15. |
| Title |
ESD Design Concepts -- Power Supply De-Coupling -- |
| Miscellaneous information |
1.16. |
| Title |
ESD Design Concepts -- Feedback Loop De-Coupling -- |
| Miscellaneous information |
1.17. |
| Title |
ESD Layout and Floorplan-Related Concepts. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
1.17.1. |
| Title |
Design Symmetry -- |
| Miscellaneous information |
1.17.2. |
| Title |
Design Segmentation -- |
| Miscellaneous information |
1.17.3. |
| Title |
ESD Design Concepts -- Utilization of Empty Space -- |
| Miscellaneous information |
1.17.4. |
| Title |
ESD Design Synthesis -- Across Chip Line Width Variation (ACLV) -- |
| Miscellaneous information |
1.17.5. |
| Title |
ESD Design Concepts -- Dummy Shapes -- |
| Miscellaneous information |
1.17.6. |
| Title |
ESD Design Concepts -- Dummy Masks -- |
| Miscellaneous information |
1.17.7. |
| Title |
ESD Design Concepts -- Adjacency -- |
| Miscellaneous information |
1.18. |
| Title |
ESD Design Concepts -- Analog Circuit Techniques -- |
| Miscellaneous information |
1.19. |
| Title |
ESD Design Concepts -- Wire Bonds -- |
| Miscellaneous information |
1.20. |
| Title |
Design Rules -- |
| Miscellaneous information |
1.20.1. |
| Title |
ESD Design Rule Checking (DRC) -- |
| Miscellaneous information |
1.20.2. |
| Title |
ESD Layout vs. Schematic (LVS) -- |
| Miscellaneous information |
1.20.3. |
| Title |
Electrical Resistance Checking (ERC) -- |
| Miscellaneous information |
1.21. |
| Title |
Summary and Closing Comments -- |
| -- |
Problems -- |
| -- |
References -- |
| Miscellaneous information |
2. |
| Title |
ESD Architecture and Floorplanning -- |
| Miscellaneous information |
2.1. |
| Title |
ESD Design Floorplan -- |
| Miscellaneous information |
2.2. |
| Title |
Peripheral I/O Design -- |
| Miscellaneous information |
2.2.1. |
| Title |
Pad-Limited Peripheral I/O Design Architecture -- |
| Miscellaneous information |
2.2.2. |
| Title |
Pad-Limited Peripheral I/O Design Architecture -- Staggered I/O -- |
| Miscellaneous information |
2.2.3. |
| Title |
Core-Limited Peripheral I/O Design Architecture -- |
| Miscellaneous information |
2.3. |
| Title |
Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- |
| Miscellaneous information |
2.3.1. |
| Title |
Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
2.3.2. |
| Title |
Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- Power Pads -- |
| Miscellaneous information |
2.4. |
| Title |
Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- Master/Slave ESD Power Clamp System -- |
| Miscellaneous information |
2.5. |
| Title |
Array I/O -- |
| Miscellaneous information |
2.5.1. |
| Title |
Array I/O -- Off-Chip Driver Banks -- |
| Miscellaneous information |
2.5.2. |
| Title |
Array I/O Nibble Architecture -- |
| Miscellaneous information |
2.5.3. |
| Title |
Array I/O Pair Architecture -- |
| Miscellaneous information |
2.5.4. |
| Title |
Array I/O -- Fully Distributed -- |
| Miscellaneous information |
2.6. |
| Title |
ESD Architecture -- Dummy Bus Architectures -- |
| Miscellaneous information |
2.6.1. |
| Title |
ESD Architecture -- Dummy VDD Bus -- |
| Miscellaneous information |
2.6.2. |
| Title |
ESD Architecture -- Dummy Ground (VSS) Bus -- |
| Miscellaneous information |
2.7. |
| Title |
Native Voltage Power Supply Architecture -- |
| Miscellaneous information |
2.7.1. |
| Title |
Single Power Supply Architecture -- |
| Miscellaneous information |
2.8. |
| Title |
Mixed-Voltage Architecture -- |
| Miscellaneous information |
2.8.1. |
| Title |
Mixed-Voltage Architecture -- Single Power Supply -- |
| Miscellaneous information |
2.8.2. |
| Title |
Mixed-Voltage Architecture -- Dual Power Supply -- |
| Miscellaneous information |
2.9. |
| Title |
Mixed-Signal Architecture -- |
| Miscellaneous information |
2.9.1. |
| Title |
Mixed-Signal Architecture -- Bipolar -- |
| Miscellaneous information |
2.9.2. |
| Title |
Mixed-Signal Architecture -- CMOS -- |
| Miscellaneous information |
2.10. |
| Title |
Mixed-System Architecture -- Digital and Analog CMOS -- |
| Miscellaneous information |
2.10.1. |
| Title |
Digital and Analog CMOS Architecture -- |
| Miscellaneous information |
2.10.2. |
| Title |
Digital and Analog Floorplan -- Placement of Analog Circuits -- |
| Miscellaneous information |
2.11. |
| Title |
Mixed-Signal Architecture -- Digital, Analog, and RF Architecture. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
2.12. |
| Title |
Summary and Closing Comments -- |
| -- |
Problems -- |
| -- |
References -- |
| Miscellaneous information |
3. |
| Title |
ESD Power Grid Design -- |
| Miscellaneous information |
3.1. |
| Title |
ESD Power Grid -- |
| Miscellaneous information |
3.1.1. |
| Title |
ESD Power Grid -- Key ESD Design Parameters -- |
| Miscellaneous information |
3.1.2. |
| Title |
ESD and the Alternative Current Path -- The Role of ESD Power Grid Resistance -- |
| Miscellaneous information |
3.2. |
| Title |
Semiconductor Chip Impedance -- |
| Miscellaneous information |
3.3. |
| Title |
Interconnect Failure and Dynamic On-Resistance -- |
| Miscellaneous information |
3.3.1. |
| Title |
Interconnect Dynamic On-Resistance -- |
| Miscellaneous information |
3.3.2. |
| Title |
Ti/Al/Ti Interconnect Failure -- |
| Miscellaneous information |
3.3.3. |
| Title |
Copper Interconnect Failure -- |
| Miscellaneous information |
3.3.4. |
| Title |
Melting Temperature of Interconnect Materials -- |
| Miscellaneous information |
3.4. |
| Title |
Interconnect Wire and Via Guidelines -- |
| Miscellaneous information |
3.4.1. |
| Title |
Interconnect Wire and Via Guidelines for HBM ESD Events -- |
| Miscellaneous information |
3.4.2. |
| Title |
Interconnect Wire and Via Guidelines for MM ESD Events -- |
| Miscellaneous information |
3.4.3. |
| Title |
Interconnect Wire and Via Guidelines for CDM ESD Events -- |
| Miscellaneous information |
3.4.4. |
| Title |
Interconnect Wire and Via Guidelines for HMM and IEC 61000-4-2 ESD Events -- |
| Miscellaneous information |
3.4.5. |
| Title |
Wire and Via ESD Metrics -- |
| Miscellaneous information |
3.5. |
| Title |
ESD Power Grid Resistance -- |
| Miscellaneous information |
3.5.1. |
| Title |
Power Grid Design -- ESD Input to Power Grid Resistance -- |
| Miscellaneous information |
3.5.2. |
| Title |
ESD Input to Power Grid Connections -- Across ESD Bus Resistance -- |
| Miscellaneous information |
3.5.3. |
| Title |
Power Grid Design -- ESD Power Clamp to Power Grid Resistance Evaluation. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
3.5.4. |
| Title |
Power Grid Design -- Resistance Evaluation -- |
| Miscellaneous information |
3.5.5. |
| Title |
Power Grid Design Distribution Representation -- |
| Miscellaneous information |
3.6. |
| Title |
Power Grid Layout Design -- |
| Miscellaneous information |
3.6.1. |
| Title |
Power Grid Design -- Slotting of Power Grid -- |
| Miscellaneous information |
3.6.2. |
| Title |
Power Grid Design -- Segmentation of Power Grids -- |
| Miscellaneous information |
3.6.3. |
| Title |
Power Grid Design -- Chip Corners -- |
| Miscellaneous information |
3.6.4. |
| Title |
Power Grid Design -- Stacking of Metal Levels -- |
| Miscellaneous information |
3.6.5. |
| Title |
Power Grid Design -- Wiring Bays and Weaved Power Bus Designs -- |
| Miscellaneous information |
3.7. |
| Title |
ESD Specification Power Grid Considerations -- |
| Miscellaneous information |
3.7.1. |
| Title |
CDM Specification Power Grid and Interconnect Design Considerations -- |
| Miscellaneous information |
3.7.2. |
| Title |
HMM and IEC Specification Power Grid and Interconnect Design Considerations -- |
| Miscellaneous information |
3.8. |
| Title |
Power Grid Design Synthesis -- ESD Design Rule Checking Methods -- |
| Miscellaneous information |
3.8.1. |
| Title |
Power Grid Design Synthesis -- ESD DRC Methods Using an ESD Virtual Design Level -- |
| Miscellaneous information |
3.8.2. |
| Title |
Power Grid Design Synthesis -- ESD DRC Methods Using an ESD Interconnect Parameterized Cell -- |
| Miscellaneous information |
3.9. |
| Title |
Summary and Closing Comments -- |
| -- |
Problems -- |
| -- |
References -- |
| Miscellaneous information |
4. |
| Title |
ESD Power Clamps -- |
| Miscellaneous information |
4.1. |
| Title |
ESD Power Clamps -- |
| Miscellaneous information |
4.1.1. |
| Title |
Classification of ESD Power Clamps -- |
| Miscellaneous information |
4.1.2. |
| Title |
Design Synthesis of ESD Power Clamp -- Key Design Parameters. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
4.2. |
| Title |
Design Synthesis of ESD Power Clamps -- |
| Miscellaneous information |
4.2.1. |
| Title |
Transient Response Frequency Trigger Element and the ESD Frequency Window -- |
| Miscellaneous information |
4.2.2. |
| Title |
The ESD Power Clamp Frequency Design Window -- |
| Miscellaneous information |
4.2.3. |
| Title |
Design Synthesis of ESD Power Clamp -- Voltage Triggered ESD Trigger Elements -- |
| Miscellaneous information |
4.3. |
| Title |
Design Synthesis of ESD Power Clamp -- The ESD Power Clamp Shunting Element -- |
| Miscellaneous information |
4.3.1. |
| Title |
ESD Power Clamp Trigger Condition vs. Shunt Failure -- |
| Miscellaneous information |
4.3.2. |
| Title |
ESD Clamp Element -- Width Scaling -- |
| Miscellaneous information |
4.3.3. |
| Title |
ESD Clamp Element -- On-Resistance -- |
| Miscellaneous information |
4.3.4. |
| Title |
ESD Clamp Element -- Safe Operating Area -- |
| Miscellaneous information |
4.4. |
| Title |
ESD Power Clamp Issues -- |
| Miscellaneous information |
4.4.1. |
| Title |
ESD Power Clamp Issues -- Power-Up and Power-Down -- |
| Miscellaneous information |
4.4.2. |
| Title |
ESD Power Clamp Issues -- False Triggering -- |
| Miscellaneous information |
4.4.3. |
| Title |
ESD Power Clamp Issues -- Pre-Charging -- |
| Miscellaneous information |
4.4.4. |
| Title |
ESD Power Clamp Issues -- Post-Charging -- |
| Miscellaneous information |
4.5. |
| Title |
ESD Power Clamp Design -- |
| Miscellaneous information |
4.5.1. |
| Title |
Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- |
| Miscellaneous information |
4.5.2. |
| Title |
Non-Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- |
| Miscellaneous information |
4.5.3. |
| Title |
ESD Power Clamp Networks with Improved Inverter Stage Feedback -- |
| Miscellaneous information |
4.5.4. |
| Title |
ESD Power Clamp Design Synthesis -- Forward Bias Triggered ESD Power Clamps. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
4.5.5. |
| Title |
ESD Power Clamp Design Synthesis -- IEC 61000-4-2 Responsive ESD Power Clamps -- |
| Miscellaneous information |
4.5.6. |
| Title |
ESD Power Clamp Design Synthesis -- Pre-Charging and Post-Charging Insensitive ESD Power Clamps -- |
| Miscellaneous information |
4.6. |
| Title |
ESD Power Clamp Design Synthesis -- Bipolar ESD Power Clamps -- |
| Miscellaneous information |
4.6.1. |
| Title |
Bipolar ESD Power Clamps with Zener Breakdown Trigger Element -- |
| Miscellaneous information |
4.6.2. |
| Title |
Bipolar ESD Power Clamps with Bipolar Transistor BVceo Breakdown Trigger Element -- |
| Miscellaneous information |
4.6.3. |
| Title |
Bipolar ESD Power Clamps with BVceo Bipolar Transistor Trigger and Variable Trigger Diode String Network -- |
| Miscellaneous information |
4.6.4. |
| Title |
Bipolar ESD Power Clamps with Frequency Trigger Elements -- |
| Miscellaneous information |
4.7. |
| Title |
Master/Slave ESD Power Clamp Systems -- |
| Miscellaneous information |
4.8. |
| Title |
Summary and Closing Comments -- |
| -- |
Problems -- |
| -- |
References -- |
| Miscellaneous information |
5. |
| Title |
ESD Signal Pin Networks Design and Synthesis -- |
| Miscellaneous information |
5.1. |
| Title |
ESD Signal Pin Structures -- |
| Miscellaneous information |
5.1.1. |
| Title |
Classification of ESD Signal Pin Networks -- |
| Miscellaneous information |
5.1.2. |
| Title |
ESD Design Synthesis of ESD Signal Devices -- Key Design Parameters -- |
| Miscellaneous information |
5.2. |
| Title |
ESD Input Structures -- ESD and Bond Pads Layout -- |
| Miscellaneous information |
5.2.1. |
| Title |
ESD and Bond Pad Layout and Synthesis -- |
| Miscellaneous information |
5.2.2. |
| Title |
ESD Structures Between Bond Pads. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
5.2.3. |
| Title |
Split I/O and Bond Pad -- |
| Miscellaneous information |
5.2.4. |
| Title |
Split ESD Adjacent to Bond Pad -- |
| Miscellaneous information |
5.2.5. |
| Title |
ESD Structures Partially Under Bond Pads -- |
| Miscellaneous information |
5.2.6. |
| Title |
ESD Structures Under and Between the Bond Pads -- |
| Miscellaneous information |
5.2.7. |
| Title |
ESD Circuits and RF Bond Pad Integration -- |
| Miscellaneous information |
5.2.8. |
| Title |
RF ESD Signal Pad Structures Under Bond Pads -- |
| Miscellaneous information |
5.3. |
| Title |
ESD Design Synthesis and Layout of MOSFETs -- |
| Miscellaneous information |
5.3.1. |
| Title |
MOSFET Key Design Parameters -- |
| Miscellaneous information |
5.3.2. |
| Title |
Single MOSFET with Silicide Block Masks -- |
| Miscellaneous information |
5.3.3. |
| Title |
Series Cascode MOSFET -- |
| Miscellaneous information |
5.3.4. |
| Title |
Triple-well MOSFETs. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
5.4. |
| Title |
ESD Design Synthesis and Layout of Diodes -- |
| Miscellaneous information |
5.4.1. |
| Title |
ESD Diode Key Design Parameters -- |
| Miscellaneous information |
5.4.2. |
| Title |
ESD Design Synthesis of Dual-Diode Networks -- |
| Miscellaneous information |
5.4.3. |
| Title |
ESD Design Synthesis of Diode String Networks -- |
| Miscellaneous information |
5.4.4. |
| Title |
ESD Design Synthesis of Back-to-Back Diode String -- |
| Miscellaneous information |
5.4.5. |
| Title |
ESD Design Synthesis for Differential Pair -- |
| Miscellaneous information |
5.5. |
| Title |
ESD Design Synthesis of SCRs -- |
| Miscellaneous information |
5.5.1. |
| Title |
ESD Design Synthesis of Uni-directional SCRs -- |
| Miscellaneous information |
5.5.2. |
| Title |
ESD Design Synthesis of Bi-directional SCRs -- |
| Miscellaneous information |
5.5.3. |
| Title |
ESD Design Synthesis of SCRs -- External Trigger Element -- |
| Miscellaneous information |
5.6. |
| Title |
ESD Design Synthesis and Layout of Resistors -- |
| Miscellaneous information |
5.6.1. |
| Title |
Polysilicon Resistor Design Layout -- |
| Miscellaneous information |
5.6.2. |
| Title |
Diffusion Resistor Design Layout -- |
| Miscellaneous information |
5.6.3. |
| Title |
P-diffusion Resistor Design Layout -- |
| Miscellaneous information |
5.6.4. |
| Title |
N-diffusion Resistor Design -- |
| Miscellaneous information |
5.6.5. |
| Title |
Buried Resistors -- |
| Miscellaneous information |
5.6.6. |
| Title |
N-well Resistors -- |
| Miscellaneous information |
5.7. |
| Title |
ESD Design Synthesis of Inductors. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
5.8. |
| Title |
Summary and Closing Comments -- |
| -- |
Problems -- |
| -- |
References -- |
| Miscellaneous information |
6. |
| Title |
Guard Ring Design and Synthesis -- |
| Miscellaneous information |
6.1. |
| Title |
Guard Ring Design and Integration -- |
| Miscellaneous information |
6.2. |
| Title |
Guard Ring Characterization -- |
| Miscellaneous information |
6.2.1. |
| Title |
Guard Ring Efficiency -- |
| Miscellaneous information |
6.2.2. |
| Title |
Guard Ring Theory -- A Generalized Bipolar Transistor Perspective -- |
| Miscellaneous information |
6.2.3. |
| Title |
Guard Ring Theory -- A Probability of Escape Perspective -- |
| Miscellaneous information |
6.2.4. |
| Title |
Guard Ring -- The Injection Ratio -- |
| Miscellaneous information |
6.3. |
| Title |
Semiconductor Chip Guard Ring Seal -- |
| Miscellaneous information |
6.4. |
| Title |
I/O to Core Guard Rings -- |
| Miscellaneous information |
6.5. |
| Title |
I/O to I/O Guard Rings -- |
| Miscellaneous information |
6.6. |
| Title |
Within I/O Guard Rings -- |
| Miscellaneous information |
6.6.1. |
| Title |
Within I/O Cell Guard Ring -- |
| Miscellaneous information |
6.6.2. |
| Title |
ESD-to-I/O OCD Guard Ring -- |
| Miscellaneous information |
6.7. |
| Title |
ESD Signal Pin Guard Rings -- |
| Miscellaneous information |
6.7.1. |
| Title |
ESD Signal Pin Guard Rings and Dual-Diode ESD Network -- |
| Miscellaneous information |
6.8. |
| Title |
Library Element Guard Rings -- |
| Miscellaneous information |
6.8.1. |
| Title |
N-channel MOSFET Guard Rings -- |
| Miscellaneous information |
6.8.2. |
| Title |
P-channel MOSFET Guard Rings -- |
| Miscellaneous information |
6.8.3. |
| Title |
RF Guard Rings -- |
| Miscellaneous information |
6.9. |
| Title |
Mixed-Signal Guard Rings -- Digital to Analog -- |
| Miscellaneous information |
6.10. |
| Title |
Mixed-Voltage Guard Rings -- High Voltage to Low Voltage. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
6.10.1. |
| Title |
Guard Rings -- High Voltage -- |
| Miscellaneous information |
6.11. |
| Title |
Passive and Active Guard Rings -- |
| Miscellaneous information |
6.11.1. |
| Title |
Passive Guard Rings -- |
| Miscellaneous information |
6.11.2. |
| Title |
Active Guard Rings -- |
| Miscellaneous information |
6.12. |
| Title |
Trench Guard Rings -- |
| Miscellaneous information |
6.13. |
| Title |
TSV Guard Rings -- |
| Miscellaneous information |
6.14. |
| Title |
Guard Ring DRC -- |
| Miscellaneous information |
6.14.1. |
| Title |
Internal Latchup and Guard Ring Design Rules -- |
| Miscellaneous information |
6.14.2. |
| Title |
External Latchup Guard Ring Design Rules -- |
| Miscellaneous information |
6.15. |
| Title |
Guard Rings and Computer Aided Design Methods -- |
| Miscellaneous information |
6.15.1. |
| Title |
Built-in Guard Rings -- |
| Miscellaneous information |
6.15.2. |
| Title |
Guard Ring Parameterized Cells -- |
| Miscellaneous information |
6.15.3. |
| Title |
Guard Ring p-Cell SKILL Code -- |
| Miscellaneous information |
6.15.4. |
| Title |
Guard Ring Resistance CAD Design Checking -- |
| Miscellaneous information |
6.15.5. |
| Title |
Post-Processing Methodology of Guard Ring Modification -- |
| Miscellaneous information |
6.16. |
| Title |
Summary and Closing Comments -- |
| -- |
Problems -- |
| -- |
References -- |
| Miscellaneous information |
7. |
| Title |
ESD Full-Chip Design Integration and Architecture -- |
| Miscellaneous information |
7.1. |
| Title |
Design Synthesis and Integration -- |
| Miscellaneous information |
7.2. |
| Title |
Digital Design -- |
| Miscellaneous information |
7.3. |
| Title |
Custom Design vs. Standard Cell Design -- |
| Miscellaneous information |
7.4. |
| Title |
Memory ESD Design -- |
| Miscellaneous information |
7.4.1. |
| Title |
DRAM Design -- |
| Miscellaneous information |
7.4.2. |
| Title |
SRAM Design -- |
| Miscellaneous information |
7.4.3. |
| Title |
Non-Volatile RAM ESD Design -- |
| Miscellaneous information |
7.5. |
| Title |
Microprocessor ESD Design. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
7.5.1. |
| Title |
3.3 V Microprocessor with 5.0 V to 3.3 V Interface -- |
| Miscellaneous information |
7.5.2. |
| Title |
2.5 V Microprocessor with 5.0 V to 2.5 V Interface -- |
| Miscellaneous information |
7.5.3. |
| Title |
1.8 V Microprocessor with 3.3 V to 1.8 V Interface -- |
| Miscellaneous information |
7.6. |
| Title |
Application-Specific Integrated Circuits -- |
| Miscellaneous information |
7.6.1. |
| Title |
ASIC ESD Design -- |
| Miscellaneous information |
7.6.2. |
| Title |
ASIC Design Gate Array Standard Cell I/O -- |
| Miscellaneous information |
7.6.3. |
| Title |
ASIC Design System with Multiple Power Rails -- |
| Miscellaneous information |
7.6.4. |
| Title |
ASIC Design System with Voltage Islands -- |
| Miscellaneous information |
7.7. |
| Title |
CMOS Image Processing Chip Design -- |
| Miscellaneous information |
7.7.1. |
| Title |
CMOS Image Processing Chip Design with Long/Narrow Standard Cell -- |
| Miscellaneous information |
7.7.2. |
| Title |
CMOS Image Processing Chip Design with Short/Wide Standard Cell -- |
| Miscellaneous information |
7.8. |
| Title |
Mixed-Signal Architecture -- |
| Miscellaneous information |
7.8.1. |
| Title |
Mixed-Signal Architecture -- Digital and Analog -- |
| Miscellaneous information |
7.8.2. |
| Title |
Mixed-Signal Architecture -- Digital, Analog, and RF -- |
| Miscellaneous information |
7.9. |
| Title |
Summary and Closing Comments -- |
| -- |
Problems -- |
| -- |
References. |
| 588 0# - |
|---|
| -- |
Print version record. |
| 590 ## - LOCAL NOTE (RLIN) |
|---|
| Local note |
eBooks on EBSCOhost |
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EBSCO eBook Subscription Academic Collection - Worldwide |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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Semiconductors |
| General subdivision |
Protection. |
| 9 (RLIN) |
272055 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Integrated circuits |
| General subdivision |
Protection. |
| 9 (RLIN) |
157189 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Electrostatics. |
| 9 (RLIN) |
157193 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Analog electronic systems |
| General subdivision |
Design and construction. |
| 9 (RLIN) |
272056 |
| 650 #6 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
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Semi-conducteurs |
| General subdivision |
Protection. |
| 9 (RLIN) |
1529783 |
| 650 #6 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Circuits intégrés |
| General subdivision |
Protection. |
| 9 (RLIN) |
1529784 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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TECHNOLOGY & ENGINEERING |
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Electronics |
| -- |
Circuits |
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General. |
| Source of heading or term |
bisacsh |
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38237 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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TECHNOLOGY & ENGINEERING |
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Electronics |
| -- |
Semiconductors. |
| Source of heading or term |
bisacsh |
| 9 (RLIN) |
886629 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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TECHNOLOGY & ENGINEERING |
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Electronics |
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bisacsh |
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886630 |
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Analog electronic systems |
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Design and construction. |
| Source of heading or term |
fast |
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(OCoLC)fst00808291 |
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272056 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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Electrostatics. |
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fast |
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(OCoLC)fst00907767 |
| 9 (RLIN) |
157193 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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Integrated circuits |
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Protection. |
| Source of heading or term |
fast |
| -- |
(OCoLC)fst00975587 |
| 9 (RLIN) |
157189 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Semiconductors |
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Protection. |
| Source of heading or term |
fast |
| -- |
(OCoLC)fst01112246 |
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Electronic books. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Display text |
Print version: |
| Main entry heading |
Voldman, Steven H. |
| Title |
ESD. |
| Place, publisher, and date of publication |
Chichester, West Sussex, U.K. : Wiley, 2011 |
| International Standard Book Number |
9780470685716 |
| Record control number |
(DLC) 2010048032 |
| -- |
(OCoLC)682892492 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
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ESD series. |
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272057 |
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